This invention relates to techniques of signal transmission between components (typically, integrated circuits) mounted within a workstation, personal computer or the like, and particularly to a technique effective for fast signal transmission.
FIG. 3 shows one example of the memory circuits used in a present workstation or personal computer.
In FIG. 3, reference numeral 30 represents memory modules each having a plurality of memory LSIs 31 mounted, and 32 a memory controller for controlling the memory LSIs 31, transmitting data being written to the memory LSIs 31 and receiving read data from the memory LSIs 31.
The memory controller 32 sometimes has separate integrated circuits which are used as a portion for controlling the memory LSIs 31 and as other portions for transmitting the data being written and receiving the read data.
The memory LSIs given above are assumed to be of the clock synchronous type. The clock synchronous type memories are, for example, SDRAMs (Synchronous Dynamic Random Access Memories).
The memory controller 32 is mounted on a mother board 33, and the memory modules 30 are also mounted on the mother board through connectors 34.
Although 8 memory modules are mounted on the mother board as shown in FIG. 3, the number of modules depends on the scale and specification of the system or the object which the user desires to achieve.
The operation of the memory circuits will be described briefly as follows. A control signal and the data signal being written from the memory controller are transmitted through a signal transmission line 35 on the mother board and through the connector 34, and a contact 36 and transmission line 37 on each memory module to the memory LSI 31 on the module. In addition, when the data is read out, the read data from the memory LSI 31 is transmitted trough the transmission line 37 and contact 36 on the module, the connector 34 and the transmission line 35 on the mother board to the memory controller 32.
This transmission line 35 is called memory bus. FIG. 3 shows only one of a plurality of memory buses.
Although the control signal and data signal are supplied to the SDRAMs as described above, a clock signal is fed thereto. The transmission line for the clock is not shown in FIG. 3. The clock transmission line is extended from the clock source directly to the memory controller and the memory LSIs within each memory module or through frequency-dividing circuits or distribution circuits thereto.
Some signal transmission lines between the integrated circuits within such a memory system are constructed by a single-phase clock system using flip-flops.
This technique is described in detail in, for example, xe2x80x9cVLSI SYSTEM DESIGN, FUNDAMENTALS OF CIRCUITS AND PACKAGINGxe2x80x9d (published by Maruzen, 1995), pp. 356-360.
FIG. 2 shows an example of the simplest single-phase clock system, in which an output circuit and an input circuit are connected in one-to-one relation through a transmission line. In FIG. 2, there are shown a circuit block 21 that includes a flip-flop 24 and the output circuit 26, and a circuit block 22 that includes the input circuit 27 and a flip-flop 25. In addition, the transmission line 23 transmits the signal from the circuit block 21 to the circuit block 22.
To the flip-flops 24 and 25 is supplied a clock directly from a clock generator or through distribution or frequency-dividing circuits from the clock generator. Although not shown in FIG. 2, generally the input signal to the flip-flop 24 is produced within the circuit block 21, and the output signal from the flip-flop 25 is supplied to another circuit within the circuit block 22.
In addition, while the input signal to the flip-flop 24 is generated within the circuit block 21 as described above, it is sometimes generated in another circuit block, and fed directly to the flip-flop. Similarly, the output signal from the flip-flop 25 is not necessarily fed to an input circuit within the circuit block 22, but it is sometimes supplied directly to an input circuit within another circuit block.
The basic operation of the circuits shown in FIG. 2 will be described below.
It is assumed that a clock is fed to the flip-flops 24 and 25. The flip-flop 24 produces in synchronism with the clock the data that has been latched at the previous cycle""s clock, and transmits it to the input portion of the output circuit 26, the output portion of which permits the data to be transmitted through the transmission line 23. The data on the transmission line 23 is fed through the input circuit 27 to the input portion of the flip-flop 25, where the data is latched in synchronism with the clock.
The single phase clock system design makes the clock of the same phase be supplied to each of the flip-flops. The equalization of the phase of the clock to one flip-flop with that to the other flip-flop is generally made by adjusting the lengths of signal lines from the clock generator or the distribution end or frequency-divider side to the clock input portion of each circuit block or by adjusting the capacitance loads of both transmission lines to the clock signal, thereby making the delay of signal in one wiring conductor equal to that in the other transmission lines.
This single-phase clock system generally employs such a high-efficient transmission method that a signal is transmitted at a cycle and latched on the receiving side at the next cycle. In this method, the cycle time, tcycle is required to satisfy the following condition.
tcycle greater than tdelay(max)+tpd(max)+tsetup(max)+tskew(max)
where the tdelay(max) is the clock access time of the circuit block 21, or the time from when the clock is fed to the circuit block 21 to when data is produced from the circuit block 21, the tpd(max) is the propagation time in which the signal produced from the circuit block 21 reaches the circuit block 22, the tsetup(max) is the setup time of the circuit block 22, or the time in which the logical value (High or Low level) of a signal to the circuit block 22 must become definite before the clock to the circuit block 22, and the tskew(max) is the clock skew between the clocks to the circuit blocks 21 and 22. The (max) in the above condition indicates the maximum of the associated value considering the dispersion of temperature and process.
In the memory circuits, when the transmission lines between the circuit blocks (the memory controller and memory modules) are relatively long, the propagation time, tpd is large. If the connector pitch is 400 mil (about 1 cm), and if sixteen memory modules are used, the propagation time tpd is 3 to 4 ns.
If the tpd(max) is 4 ns and if the cycle rate is 33 MHz, the ratio of the tpd to the period, 30 ns is only about 0.1, and thus the condition of
tcycle greater than tdelay(max)+tpd(max)+tsetup(max)+tskew(max)
can be satisfied by fast operation of the circuit blocks.
However, if the cycle rate is increased to 250 MHz, the period is equal to the tpd(max), or 4 ns. Thus, even though the circuit blocks are operated at higher speed, this system cannot be realized. Since the tdelay (max), tsetup (max) and tskew(max) can be decreased by reducing the size of devices, the condition of
tcycle less than tdelay(max)+tpd(max)+tsetup(max)+tskew(max)
can be actually satisfied even at around 100 MHz, not 200 MHz. Thus, the circuit blocks cannot be operated at a higher cycle rate than 100 MHz from the design point of view.
For faster operation, there is a consideration of ensuring window, that is a signal valid interval, other than the above delay calculation. Although the delay calculation considers whether signal transmission is possible or not under the condition that the phase of clock to the output circuit is made equal to that of the clock to the input circuit, the window consideration enables much higher operation by adding offset adjustment to the clock phase.
The addition of offset adjustment to the clock phase means that, for example in FIG. 3, the phase of the clock to the memory modules is deviated ahead of or behind that of the clock to the memory controller.
If the write delay time is shorter than the read delay time, the cycle rate is determined according to the read delay time under the delay calculation method. In the window consideration case, the phase of the clock to the memory LSI is deviated to proceed, making the read data be fast produced. Consequently, the above result increases the time between the clock edge at the memory LSI and the clock edge at the next cycle to memory controller, thus ensuring a longer time than read delay time. In other words, when the window time assurance is considered, the window time twindow, or
twinodw=tcycle+tOHxe2x88x92tdelay(max)
is used to design in place of the above condition.
The tOH is the data output hold time in which the output from the output circuit block that is producing an output signal at a clock is switched, after the next clock is fed, to the data (of its cycle). This time is equal to the tdelay(min), namely the minimum value of tdelay or the above.
Under the estimated value of twindow, it is necessary to satisfy the following condition.
twindow greater than tpd(maxxe2x88x92min)+tsetup(max)+thold(max)
where the tpd(maxxe2x88x92min) is the difference between the maximum and minimum of tpd. In FIG. 3, the maximum is the propagation time between the memory controller and the farthest module, and the minimum is the propagation time between the memory controller and the nearest module. In other words, the tdelay(maxxe2x88x92min) indicates the propagation time difference depending on the position of the memory modules.
If the window time is considered for the data writing time and reading time to and from the memory modules, and if the condition of
twindow greater than tpd(maxxe2x88x92min)+tsetup(max)+thold(max)
is satisfied, then it is necessary to set up the offset values of the clock phases so that the setup time and hold time can be ensured in the twindowxe2x88x92tpd(maxxe2x88x92min).
This method enables the operation to be slightly increased, but when the system size, for example, the number of the mounted modules as in FIG. 3 is increased, the tpd(maxxe2x88x92min) cannot be neglected, and thus it is still difficult to increase the operation speed.
That is, demand for faster transmission increases the effect of the difference between the propagation time in which the signal from the memory controller is transmitted to the nearest memory module and the propagation time in which the signal from the memory controller is transmitted to the farthest memory module. Consequently, it is difficult to design a memory system for faster operation.
The same problem occurs not only in the memory system but also in the signal transmission between the circuits for transmitting and receiving signals in synchronism with a clock, for example, in the processor bus of a multiprocessor system using a plurality of microprocessors.
This invention is to solve these problems in the system for transmitting and receiving signals in synchronism with a clock signal.
It is an object of the invention to provide a signal transmission system capable of removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.
Other objects of the invention will be cleared by the following descriptions.
According to the present invention, to achieve the above objects, there is provided a signal transmission system including a clock output circuit for producing a clock signal, a first circuit block for producing a first signal, a plurality of second circuit blocks for receiving the clock signal, a circuit board having the plurality of second circuit blocks mounted in a row, a first wiring conductor for transmitting the clock signal, and a second transmission line for transmitting signals from the first circuit block to the second circuit blocks, wherein the first transmission line is laid out from the clock output circuit to the plurality of second circuit blocks, and connected thereto in series, and the second transmission line is laid out from the first circuit block to the second circuit blocks, and connected thereto in series, thus the first and second transmission lines being connected to the second circuit blocks.
Therefore, the distance that the clock signal is transmitted from the clock output circuit to an arbitrary one of the second circuit blocks and the distance that the first signal is transmitted from the first circuit block to the second circuit blocks are substantially the same. Thus, when the second circuit blocks latch the first signal in synchronism with the clock signal, it is possible to suppress the effect of the propagation delay of the first signal between the circuits.
In addition, the first and second transmission lines are each laid out from the first circuit block to the farthest one of the second circuit blocks or more distance position, and turned back therefrom, extending back to the nearest one of the second circuit blocks to the first circuit block to form forward and backward transmission line portions, and some of the second circuit blocks are connected to the forward portions of the first and second transmission lines, the remaining second circuit blocks being connected to the backward portions of the first and second transmission lines, thereby reducing the density of the loads.
Moreover, there is provided a signal transmission system including a clock output circuit for producing a clock signal, a first circuit block for producing a first signal and receiving a second signal, a plurality of second circuit blocks for receiving the first signal and producing the second signal, a circuit board having the plurality of second circuit blocks mounted in a row, a first transmission lines for transmitting the clock signal, a second transmission line for transmitting a signal from the first circuit block to the second circuit blocks, and a third transmission line for transmitting a signal from the second circuit blocks to the first circuit block, wherein the first transmission line is laid out from the clock output circuit to the plurality of second circuit blocks, and connected thereto in series, the second and third transmission lines are laid out from the first circuit block to the plurality of second circuit blocks, and connected thereto in series, the second transmission line is laid out from the first circuit block to the farthest one of the second circuit blocks or more distant position, and turned back therefrom, extending back to the nearest one of the second circuit blocks to the first circuit block to form forward and backward transmission line portions, the first and third transmission lines are laid out from the first circuit block to the farthest one of the second circuit blocks or more distant position, turned back therefrom, extending back to the nearest one of the second circuit blocks to the first circuit block, and then reach the first circuit block to form forward and backward transmission line portions, some of the second circuit blocks are connected to the forward portions of the first and second transmission lines, the remaining second circuit blocks being connected to the backward portions of the first and second transmission lines, and the some of the second circuit blocks connected to the forward portion of the first transmission line are connected to the backward portion of the third transmission line, the remaining second circuit blocks being connected to the forward portion of the third transmission line.
Therefore, the relation of the distance that the clock signal is transmitted to an arbitrary one of the second circuit blocks to the distance that the first signal is transmitted from the first output circuit to the second circuit blocks, and the relation of the distance that the second signal produced from the second circuit blocks in synchronism with the clock signal reaches the first circuit block to the distance that the clock signal at which the second circuit blocks produce the second signal reaches the first circuit block are substantially constant independently of the positions of the mounted second circuit blocks. In addition, when the second circuit blocks latch the first signal in synchronism with the clock signal, and when the first circuit block latches the second signal, it is possible to suppress the effect of the propagation delay of first and second signals between the circuits.
Also, there is provided a signal transmission system including a first circuit block that has a first output circuit for producing a first signal, a second output circuit for producing a second signal, a first receiving circuit for receiving a third signal, and a second receiving circuit for receiving a fourth signal, a plurality of second circuit blocks each of which has a third receiving circuit for receiving the first signal, a fourth receiving circuit for receiving the second signal, a third output circuit for producing the third signal, and a fourth output circuit for producing the fourth signal, and first, second, third and fourth transmission line for transmitting first, second, third and fourth signals between the first circuit block and the second circuit blocks, wherein the first, second, third and fourth transmission lines are laid out from the first circuit block to the farthest one of the second circuit blocks or more distance place, and turned back therefrom to form forward and backward conductor portions, some of the second circuit blocks are connected to the forward portions for the first and third signals, the remaining second circuit blocks being connected to the backward transmission line portions, the some of the second circuit blocks connected to the forward portion for the first signal are connected to the backward portions for the second and fourth signals, and the other second circuit blocks are connected to the forward transmission line portions, the second receiving circuit latches the fourth signal in synchronism with the third signal, and the fourth receiving circuit latches the fourth signal in synchronism with the first signal. When the second circuit blocks produce data, the first circuit block may produce a timing signal at which the data is received.